The continuing demand for higher speed and lower cost semiconductor memories has led to the development of the virtual ground configuration for read-only type memories. Virtual ground memories are a well-known technique for increasing the array density while at the same time maintaining process compatibility with existing double-level polysilicon n-channel processes. Virtual ground memories are disclosed in U.S. Pat. Nos. 3,916,169; 3,934,233; 4,021,781 and 4,387,447.
While virtual ground memories do enjoy an advantage from the perspective of increased bit density, they are not without their disadvantages. For instance, virtual ground memory arrays normally require extensive and somewhat complex decode circuitry which unfortunately occupies a very large amount of space on the chip. There also exists the problem of unwanted interaction of adjacent cells. That is, unintentional disturbance of adjacent cells may result from operations on a single bit or cell. Interaction between adjacent cells also causes parasitic currents which interfere with the reading, erasing and programming of individual cells. Ultimately, the access time and speed of the memory is adversely affected by this problem.
At least part of the reason for the adjacent cell disturbance phenomena inherently lies in the organization of prior art electrically programmable read-only memory (EPROM) arrays. Conventionally, a virtual ground EPROM array is organized as a plurality of words containing 8-bits each (8-bits forming a data byte). The array may be organized such that individual blocks only store the information from one data bit (e.g., b0) taken from a plurality of bytes, e.g., bytes 0-8. The most important characteristic of prior art arrays for purposes of this invention is that data bits within the array are read, erased and programmed individually. In other words, bits are addressed and read one bit at a time.
In an attempt to mitigate the problem of unintentional interaction of adjacent cells, an asymmetrically lightly-doped source (ALDS) cell was recently proposed in an article entitled "An Asymmetrical Lightly-Doped Source (ALDS) Cell For Virtual Ground High-Density EPROMs", by K. Yoshikawa et al. IEDM, 1988, pp. 432-435. The key feature of the ALDS cell is a lightly-doped n- source region which is coupled to each column in the array. As shown in FIG. 1 of the Yoshikawa paper, adjacent cells have their drains coupled to the same column line as the n- diffusion. While the authors of the above-mentioned article do report a resistance to write disturbs in virtual ground designs, ALDS virtual ground arrays still exhibit significant unwanted interaction between adjacent cells. Moreover, precharging mode for the proposed ALDS structure in virtual ground high-density EPROMs is somewhat limited.
To overcome the drawbacks associated with prior art virtual ground architectures, the present invention provides a virtual ground EPROM array in which bits from two or more data bytes are combined in a single block. According to the teachings of the present invention, a single address accesses two adjacent bits within a block (e.g., bits b0 and b1) simultaneously. The architecture of the presently invented EPROM array markedly suppresses parasitic currents and unintentional disturbance of neighboring cells.
Additionally, the present invention permits quicker access time and faster overall operating speed within the memory array. As will be seen, the present invention also supports flash erase operations.